Datasheet

Table Of Contents
The lower blocks in the NVM main address space can be allocated as a boot loader section by using the
BOOTPROT fuses, and the upper rows can be allocated to EEPROM.
The NVM memory is separated into six parts:
1. CB space
Contains factory calibration and system configuration information.
Address; 0x00800000
Size: 1 page
Property: Read-Only
2. FS space
Contains the factory signature information.
Address; 0x00806000
Size: 4 pages
Property: Read-Only.
3. USER space
Contains user defined startup configuration. The first word is reserved, and used during the
NVMCTRL start-up to automatically configure the device.
Address: 0x00804000
Size: 1 page
Property: Read-Write
4. Main address space
The main address space is divided into 32 equally sized regions. Each region can be protected
against write or erase operation. The 32-bit RUNLOCK register reflects the protection of each
region. This register is automatically updated after power-up with the region lock user fuse data; To
lock or unlock a region, the LR or UR commmands can be issued.
Address: 0x00000000
Size: PARAM.NVMP pages.
Property: Read-Write
5. Bootloader space
The bootloader section starts at the beginning of the main address space; Its size is defined by the
BOOTPROT[3:0] fuse. It is protected against write or erase operations, except if STATUS.BPDIS is
set. Issuing a write or erase command at an address inside the BOOTPROT section sets
STATUS.PROGE and STATUS.LOCKE. STATUS.BPDIS can be set by issuing the Set BOOTPROT
Disable command (SBPDIS). It is cleared by issuing the Clear BOOTPROT Disable command
(CBPDIS). This allows to program an new bootloader without changing the user page and issuing a
new NVMCTRL startup sequence to reload the user configuration. The BOOTPROT section is not
erased during a Chip-Erase operation even if STATUS.BPDIS is high.
Address: 0x00000000
Size: (15 - STATUS.BOOTPROT) × 8192
Property: Read-Only.
6. SmartEEPROM raw data space
The SmartEEPROM algorithm emulates an EEPROM with a portion of the NVM main. Smart-
EEPROM raw data is mapped at the end of the main address space. SmartEEPROM allocated
space in the main address space is not accessible from AHB0/1. Any AHB access throws a
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 643