Datasheet

25.6 Functional Description
25.6.1 Principle of Operation
The NVM Controller is a slave on the AHB (AHB0, AHB1 and AHB2) and APB buses. It responds to
commands, read requests and write requests, based on user configuration. AHB0 and AHB1 allow
access to the NVM main address space, the auxiliarry space and the page buffer. AHB2 provides access
to the SmartEEPROM interface that indirecly accesses the reserved area in the NVM for EEPROM
emulation.
25.6.1.1 Initialization
After power-up, the NVM Controller goes through a power-up sequence. During this time, access to the
NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is
operational without any need for user configuration.
25.6.1.2 Software Reset
Software reset is triggered by the SWRST command, and does the following:
• NVM (physical memory) reset
• Device power-up sequence (redo the device calibration)
• Reset all APB configuration registers (and status)
Note:
STATUS.READY goes low when the SWRST command starts to execute.
STATUS.READY goes high when the SWRST command has completed.
Any AHB0/1/2 access is stalled until the command has completed.
25.6.2 Memory Organization
Memory space is divided in two:
• The main address space where 2 physical NVM banks (BANKA and BANKB) are mapped.
• The auxiliary space which contains:
– The User page (USER)
– The calibration page (CB)
– Factory and signature pages (FS)
BANKA and BANKB can be swapped in the address space. For more information, see Memory Bank
Swapping.
Refer to the Physical Memory Map for memory sizes and addresses for each device.
BANKA, BANKB and AUX pages have different erase and write granularities, see the table below.
Table 25-2. Erase and Write granularity
Erase Granularity Write Granularity
BANKA Block Quad-Word or Page
BANKB Block Quad-Word or Page
AUX Page Quad-Word
The NVM is organized into two banks, each bank is organized into blocks, where each block contains
sixteen pages.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 642