Datasheet

Table Of Contents

proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to

be used for a particular frequency range. Automatic wait state generation can be use by setting the Auto

Wait State bit in the Control A register (NVMCTRL.CTRLA.AUTOWS). Alternatively a custom

programmable number of wait states can be set by writing the NVM Read Wait State bits

(NVMCTRL.CTRLA.RWS) to optimize performance.

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25.8.1 CTRLA

25.5.3 DMA

The NVMCTRL supports AHB burst transfers. It is possible to write the page buffer in sequence without

AHB rearbitration in case of concurrent AHB writes to the page buffer to guarantee data integrity.

25.5.4 Interrupts

The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL

interrupt requires the interrupt controller to be programmed first.

25.5.5 Debug Operation

When the CPU is halted in debug mode, the ECC feature of the NVMCTRL will correct and log ECC

errors based on the table below.

Table 25-1. ECC Debug Operation

DBGCTRL.ECCELOG DBGCTRL.ECCDIS DBGCTRL.ECCDIS

0 0 ECC errors from debugger reads are corrected, but not

logged in INTFLAG.

1 0 ECC errors from debugger reads are corrected and

logged in INTFLAG.

X 1 ECC errors from debugger reads are neither corrected

nor logged in INTFLAG.

Reading the SmartEEPROM configured in buffered mode with a debugger is intrusive, since the

pagebuffer must be flushed when the read is performed in a page under modification.

Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be

accessible. See the section on the NVMCTRL 25.6.10 Security Bit for details.

25.5.6 Register Access Protection

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC),

except the Interrupt Flag Status and Clear register (INTFLAG).

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write

Protection" property in each individual register description.