Datasheet

Address Core Peripheral
0xE000E008-0xE000E00F System control block
0xE000E010-0xE000E01F System timer
0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller
0xE000ED00-0xE000ED3F System control block
0xE000ED90-0xE000ED93 MPU Type Register
0xE000ED90-0xE000EDB8 Memory Protection Unit
0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller
0xE000EF30-0xE000EF44 Floating Point Unit
Related Links
8. Product Memory Mapping Overview
10.2 Nested Vector Interrupt Controller
10.2.1 Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM D5x/E5x family devices supports 138
interrupts with eight different priority levels. For more details, refer to the Cortex-M4 Technical Reference
Manual (http://www.arm.com).
10.2.2 Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have many interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be
individually enabled by writing a '1' to the corresponding bit in the peripheral’s Interrupt Enable Set
(INTENSET) register, and disabled by writing '1' to the corresponding bit in the peripheral’s Interrupt
Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding
interrupt is enabled.
Depending on their criticality, the interrupt requests for one peripheral are either ORed together on
system level, generating one interrupt or directly connected to an NVIC interrupt lines. This is described
in the table below.
An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending
registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/
CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for
each interrupt.
Module Source Line
EIC NMI - External Interrupt Control NMI NMI
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 64