Datasheet

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Features Cortex-M4 Options SAM D5x/E5x Configuration
Debug support level 0 = No debug. No DAP, breakpoints,
watchpoints, Flash patch, or halting debug.
1 = Minimum debug. Two breakpoints, one
watchpoint, no Flash patch.
2 = Full debug minus DWT data matching.
3 = Full debug plus DWT data matching.
3 = Full debug plus DWT data
matching.
Trace support level 0 = No trace. No ETM, ITM or DWT triggers and
counters.
1 = Standard trace. ITM and DWT triggers and
counters, but no ETM.
2 = Full trace. Standard trace plus ETM.
3 = Full trace plus HTM port.
2 = Full trace. ITM, TPIU, ETM,
and DWT triggers and
counters are present. HTM
port is not present
JTAG Present or Not present Not present
Bit Banding Present or Not present Not present
FPU Present or Not present Present
10.1.4 Cortex-M4 Core Peripherals
Nested
Vectored
Interrupt
Controller
The Nested Vector Interrupt Controller (NVIC) is an embedded interrupt controller
that supports low latency interrupt processing.
System Control
Block
The System Control Block (SCB) is the programmers model interface to the
processor. It provides system implementation information and system control,
including configuration, control, and reporting of system exceptions. Refer to the
Cortex-M4 Technical Reference Manual for details (http://www.arm.com).
System Timer The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real-Time
Operating System (RTOS) tick timer or as a simple counter. The SysTick timer runs
on the processor clock and it does not decrement when the processor is halted for
debugging. Refer to the Cortex-M4 Technical Reference Manual for details (http://
www.arm.com).
Memory
Protection Unit
The Memory Protection Unit (MPU) improves system reliability by defining the
memory attributes for different memory regions. It provides up to eight different
regions, and an optional predefined background region. Refer to the Cortex-M4
Technical Reference Manual for details (http://www.arm.com).
Floating-Point
Unit
The Floating Point Unit (FPU) provides IEEE 754-compliant operations on single-
precision, 32-bit, floating-point values. Refer to the Cortex-M4 Technical Reference
Manual for details (http://www.arm.com).
10.1.5 Cortex-M4 Address Map
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 63