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Datasheet

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Table Of Contents
24.9.84 GMAC 1588 Timer Seconds Low Register
Name:  TSL
Offset:  0x1D0
Reset:  0x00000000
Property:  Read/Write
Bit 31 30 29 28 27 26 25 24
TCS[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
TCS[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TCS[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – TCS[31:0] Timer Count in Seconds
This register is writable. It increments by 1 when the IEEE 1588 nanoseconds counter counts to one
second. It may also be incremented when the Timer Adjust Register is written.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 621