Datasheet

10.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system
visibility of the processor and memory through a 2-pin Serial Wire Debug (SWD) port that is ideal for
microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. The Embedded Trace Macrocell (ETM) delivers unrivaled instruction
trace capture in an area far smaller than traditional trace units, enabling many low cost MCUs to
implement full instruction trace for the first time.
To enable simple and cost-effective profiling of the system events these generate, a stream of software-
generated messages, data trace, and profiling information is exported over three different ways:
• Output off chip using the TPIU, through a single pin, called Serial Wire Viewer (SWV). Limited to ITM
system trace
• Output off chip using the TPIU, through a 4-bit pin interface. Bandwidth is limited
• Internally stored in RAM, using the CoreSight ETB. Bandwidth is then optimal but capacity is limited
The Flash Patch and Breakpoint Unit (FPB) provides up to 8 hardware breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to 8 words in the
program code in the CODE memory region. This enables applications stored on a non-erasable, ROM-
based microcontroller to be patched if a small programmable memory, for example flash, is available in
the device. During initialization, the application in ROM detects, from the programmable memory, whether
a patch is required. If a patch is required, the application programs the FPB to remap a number of
addresses. When those addresses are accessed, the accesses are redirected to a remap table specified
in the FPB configuration, which means the program in the non-modifiable ROM can be patched.
10.1.3 Cortex-M4 Processor Features and Configuration
• Thumb
®
instruction set combines high code density with 32-bit performance
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Integrated sleep modes for low power consumption
• Fast code execution permits slower processor clock or increases Sleep mode time
• Hardware division and fast digital-signal-processing orientated multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Memory Protection Unit (MPU) for safety-critical applications
• Extensive debug and trace capabilities: Serial Wire Debug and Serial Wire Trace reduce the number
of pins required for debugging, tracing, and code profiling.
Features Cortex-M4 Options SAM D5x/E5x Configuration
Interrupts 1 to 240 138
Number of priority
bits
3 to 8 3 = eight levels of priority
Data endianness Little-endian or big-endian Little-endian
SysTick Timer
calibration value
0x80000000
MPU Present or Not present Present
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 62