Datasheet

10. Processor and Architecture
10.1 Cortex M4 Processor
The ARM
®
Cortex
™
-M4 processor is a high performance 32-bit processor designed for the microcontroller
market. It offers the following significant benefits to developers:
• Outstanding processing performance combined with fast interrupt handling
• Enhanced system debug with extensive breakpoint and trace capabilities
• Efficient processor core, system and memories
• Ultra low-power consumption with integrated sleep modes
• Platform security robustness, with integrated memory protection unit (MPU).
The implemented ARM Cortex-M4 is revision r0p1
For additional information, refer to http://www.arm.com
The Cortex-M4 processor is built on a high-performance processor core with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional
power efficiency through an efficient instruction set and extensively optimized design, providing high-end
processing hardware including IEEE 754-compliant single-precision floating-point computation, a range of
single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M4 processor implements a version of the Thumb instruction set
based on Thumb
®
-2 technology, ensuring high code density and reduced program memory requirements.
The Cortex-M4 instruction set provides the exceptional performance expected of a modern 32-bit
architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt
performance. The NVIC includes a Non-Maskable interrupt (NMI), and provides up to 8 interrupt priority
levels. The tight integration of the processor core and NVIC provides fast execution of Interrupt Service
Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware
stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt
handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-
chain optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep
function that enables the entire device to be rapidly powered down while still retaining program state.
10.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA technology to provide high-speed,
low-latency memory accesses. It supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data
handling.
The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain memory control,
enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on
a task-by-task basis. Such requirements are becoming critical in many embedded applications such as
automotive.
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 61