Datasheet

24.9.37 GMAC Octets Transmitted Low Register
Name: OTLO
Offset: 0x100
Reset: 0x00000000
Property: Read-Only
When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to
bits [47:32] to ensure reliable operation.
Bit 31 30 29 28 27 26 25 24
TXO[31:24]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
TXO[23:16]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TXO[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TXO[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – TXO[31:0] Transmitted Octets
Transmitted octets in valid frames of any type without errors, bits [31:0]. This counter is 48-bits, and is
read through two registers. This count does not include octets from automatically generated pause
frames.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 574