Datasheet

9.3 SRAM Memory Configuration
Retention
Depending on the application and power budget needs, part of the system memory can be retained in
Standby or Hibernate sleep modes. The amount of the SRAM retained in this mode is software
selectable, by writing the RAMCFG bits in the Power Manager Standby Configuration register and
Hibernate Configuration register respectively (STDBYCFG.RAMCFG and HIBCFG.RAMCFG).
By default, the entire system memory section is retained, but no retention or bottom 32KB memory
retention options are also available.
Figure 9-1. Retention Options
0x20000000
Full Memory
Retention
32 KB
Retention
No Memory
Retention
0 KB
32 KB
Full SRAM Size
RAM Error Correction
For safety applications, the SAM D5x/E5x family embeds error correction codes (ECC) to detect and
correct single bit errors, or to enable dual error detection for the system memory. The ECC is software
selectable through the RAM ECCDIS bit in the NVM User Row. For additional information, refer to Table
9-2.
When enabled, the top half system memory will be reserved to store the ECC, and will not be available
for the application.
SAM D5x/E5x Family Data Sheet
Memories
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 55