Datasheet

Bit 31 30 29 28 27 26 25 24
WZO CLTTO OP[1:0] PHYA[4:1]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PHYA[0:0] REGA[4:0] WTN[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 31 – WZO Write ZERO
Must be written to '0'.
Value Description
0
Mandatory
1
Reserved
Bit 30 – CLTTO Clause 22 Operation
Value Description
0
Clause 45 operation
1
Clause 22 operation
Bits 29:28 – OP[1:0] Operation
Value Description
01
Write
10
Read
Other
Reseved
Bits 27:23 – PHYA[4:0] PHY Address
Bits 22:18 – REGA[4:0] Register Address
Specifies the register in the PHY to access.
Bits 17:16 – WTN[1:0] Write Ten
Must be written to '10'.
Value Description
10
Mandatory
Other
Reserved
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 549