Datasheet

24.9.14 GMAC PHY Maintenance Register
Name: MAN
Offset: 0x034
Reset: 0x00000000
Property: Read/Write
This register is a shift register. Writing to it starts a shift operation which is signaled completed when bit 2
is set in the Network Status Register (NSR). It takes about 2000 MCK cycles to complete, when MDC is
set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon
completion.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO
pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Refer also to
section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation returns the current contents of the shift register. At the end of
management operation, the bits will have shifted back to their original locations. For a read operation, the
data bits are updated with data read from the PHY. It is important to write the correct values to the register
to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs, as well as clause 22 PHYs. To read clause 45
PHYs, bit 30 should be written with a '0' rather than a '1'. To write clause 45 PHYs, bits 31:28 should be
written as 0x1:
PHY Access Bit Value
WZO CLTTO OP[1] OP[0]
Clause 22 Read 0 1 1 0
Write 0 1 0 1
Clause 45 Read 0 0 1 1
Write 0 0 0 1
Read + Address 0 0 1 0
For a description of MDC generation, see also the 'GMAC Network Configuration Register' (NCR)
description.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 548