Datasheet

24.9.10 GMAC Interrupt Status Register
Name: ISR
Offset: 0x024
Reset: 0x00000000
Property: -
This register indicates the source of the interrupt. An interrupt source must be enabled in the mask
register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be
asserted in the system.
Bit 31 30 29 28 27 26 25 24
TSUCMP WOL SRI PDRSFT PDRQFT
Access
W R R R R
Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PDRSFR PDRQFR SFT DRQFT SFR DRQFR
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PFTR PTZ PFNZ HRESP ROVR
Access
R R R R R
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 29 – TSUCMP TSU Timer Comparison
Indicates TSU times count and comparison value are equal.
Bit 28 – WOL Wake On LAN
WOL interrupt. Indicates a WOL message has been received.
Bit 26 – SRI TSU Seconds Register Increment
Indicates the register has incremented.
Cleared on read.
Bit 25 – PDRSFT PDelay Response Frame Transmitted
Indicates a PTP pdelay_resp frame has been transmitted.
Cleared on read.
Bit 24 – PDRQFT PDelay Request Frame Transmitted
Indicates a PTP pdelay_req frame has been transmitted.
Cleared on read.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 539