Datasheet

24.9.9 GMAC Receive Status Register
Name: RSR
Offset: 0x020
Reset: 0x00000000
Property: -
This register, when read, provides receive status details. Once read, individual bits may be cleared by
writing a '1' to them. It is not possible to set a bit to '1' by writing to this register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
HNO RXOVR REC BNA
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – HNO HRESP Not OK
This bit is set when the DMA block sees HRESP not OK.
This bit is cleared by writing a '1' to it.
Bit 2 – RXOVR Receive Overrun
This bit is set if the receive status was not taken at the end of the frame. The buffer will be recovered if an
overrun occurs.
This bit is cleared by writing a '1' to it.
Bit 1 – REC Frame Received
This bit is set to when one or more frames have been received and placed in memory.
This bit is cleared by writing a '1' to it.
Bit 0 – BNA Buffer Not Available
When this bit is set, an attempt was made to get a new buffer and the pointer indicated that it was owned
by the processor. The DMA will re-read the pointer each time an end of frame is received until a valid
pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive
pointers are unsuccessful and software has in the mean time cleared the status flag.
This bit is cleared by writing a '1' to it.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 538