Datasheet

24.9.7 GMAC Receive Buffer Queue Base Address Register
Name: RBQB
Offset: 0x018
Reset: 0x00000000
Property: Read/Write
This register holds the start address of the receive buffer queue (receive buffers descriptor list). The
receive buffer queue base address must be initialized before receive is enabled through bit 2 of the
Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base
Address Register is ignored. Reading this register returns the location of the descriptor currently being
accessed. This value increments as buffers are used. Software should not use this register for
determining where to remove received frames from the queue as it constantly changes as new frames
are received. Software should instead work its way through the buffer descriptor queue checking the
“used” bits.
In terms of AMBA AHB operation, the descriptors are read from memory using a single 32-bit AHB
access. The descriptors should be aligned at 32-bit boundaries and the descriptors are written to using
two individual non sequential accesses.
Bit 31 30 29 28 27 26 25 24
ADDR[29:22]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
ADDR[21:14]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ADDR[13:6]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[5:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 31:2 – ADDR[29:0] Receive Buffer Queue Base Address
Written with the address of the start of the receive queue.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 536