Datasheet

Table Of Contents

In DMA packet buffer mode, this bit is also set if a single frame is too large for the configured packet

buffer memory size.

This bit is cleared by writing a '1' to it.

Bit 3 – TXGO Transmit Go

This bit is '1' when transmit is active. When using the DMA interface this bit represents the TXGO variable

as specified in the transmit buffer description.

Bit 2 – RLE Retry Limit Exceeded

This bit is cleared by writing a '1' to it.

Bit 1 – COL Collision Occurred

When operating in 10/100Mbps mode, this bit is set by the assertion of either a collision or a late collision.

This bit is cleared by writing a '1' to it.

Bit 0 – UBR Used Bit Read

This bit is set when a transmit buffer descriptor is read with its used bit set.

This bit is cleared by writing a '1' to it.

SAM D5x/E5x Family Data Sheet

GMAC - Ethernet MAC

Datasheet

DS60001507E-page 535