Datasheet

24.9.6 GMAC Transmit Status Register
Name: TSR
Offset: 0x014
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
HRESP
Access
R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
UND TXCOMP TFC TXGO RLE COL UBR
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 8 – HRESP HRESP Not OK
Set when the DMA block sees HRESP not OK.
This bit is cleared by writing a '1' to it.
Bit 6 – UND Transmit Underrun
This bit is set if the transmitter was forced to terminate the transmission of a frame due to further data
being unavailable.
This bit is also set if a transmitter status write back has not completed when another status write back is
attempted.
When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit
DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further
data, or an AHB not OK response was returned, or a used bit was read.
This bit is cleared by writing a '1' to it.
Bit 5 – TXCOMP Transmit Complete
Set when a frame has been transmitted.
This bit is cleared by writing a '1' to it.
Bit 4 – TFC Transmit Frame Corruption Due to AHB Error
This bit is set when an error occurs during reading transmit frame from the AHB. Error causes include
HRESP errors and buffers exhausted mid frame. (If the buffers run out during transmission of a frame
then transmission stops, FCS shall be bad and GTXER asserted).
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 534