Datasheet

When writing a '1' to this bit, the back-off between collisions will always be one slot time. This setting
helps testing the too many retries condition. This setting is also useful for pause frame tests by reducing
the pause counter's decrement time from "512 bit times" to "every GRXCK cycle".
Bit 8 – MAXFS 1536 Maximum Frame Size
Writing a '1' to this bit increases the maximum accepted frame size to 1536 bytes in length. When written
to '0', any frame above 1518 bytes in length is rejected.
Bit 7 – UNIHEN Unicast Hash Enable
When writing a '1' to this bit, unicast frames will be accepted when the 6-bit hash function of the
destination address points to a bit that is set in the Hash Register.
Writing a '0' to this bit disables unicast hashing.
Bit 6 – MTIHEN Multicast Hash Enable
When writing a '1' to this bit, multicast frames will be accepted when the 6-bit hash function of the
destination address points to a bit that is set in the Hash Register.
Writing a '0' to this bit disables multicast hashing.
Bit 5 – NBC No Broadcast
Writing a '1' to this bit will reject frames addressed to the broadcast address 0xFFFFFFFFFFFF (all '1').
Writing a '0' to this bit allows broadcasting to 0xFFFFFFFFFFFF.
Bit 4 – CAF Copy All Frames
When writing a '1' to this bit, all valid frames will be accepted.
Bit 3 – JFRAME Jumbo Frame Size
Writing a '1' to this bit enables jumbo frames of up to 10240 bytes to be accepted. The default length is
10240 bytes.
Bit 2 – DNVLAN Discard Non-VLAN Frames
Writing a '1' to this bit allows only VLAN-tagged frames to pass to the address matching logic.
Writing a '0' to this bit allows both VLAN_tagged and untagged frames to pass to the address matching
logic.
Bit 1 – FD Full Duplex
Writing a '1' enables full duplex operation, so the transmit block ignores the state of collision and carrier
sense and allows receive while transmitting.
Writing a '0' disables full duplex operation.
Bit 0 – SPD Speed
Writing a '1' selects 100Mbps operation.
Writing a '0' to this bit selects 10Mbps operation.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 528