Datasheet

Bit 24 – RXCOEN Receive Checksum Offload Enable
Writing a '1' to this bit enables the receive checksum engine, and frames with bad IP, TCP or UDP
checksums are discarded.
Bit 23 – DCPF Disable Copy of Pause Frames
Writing a '1' to this bit prevents valid pause frames from being copied to memory. Pause frames are not
copied regardless of the state of the Copy All Frames (CAF) bit, whether a hash match is found or
whether a type ID match is identified.
If a destination address match is found, the pause frame will be copied to memory. Note that valid pause
frames received will still increment pause statistics and pause the transmission of frames, as required.
Bits 22:21 – DBW[1:0] Data Bus Width
The default value for this register is 64 bits.
Value Name Description
0
DBW32 32-bit data bus width
1
DBW64 64-bit data bus width
Bits 20:18 – CLK[2:0] MDC Clock Division
These bits must be set according to MCK speed, and determine the number MCK will be divided by to
generate Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not
exceed 2.5MHz.
Note: MDC is only active during MDIO read and write operations.
Value Name Description
0
MCK_8 MCK divided by 8 (MCK up to 20MHz)
1
MCK_16 MCK divided by 16 (MCK up to 40MHz)
2
MCK_32 MCK divided by 32 (MCK up to 80MHz)
3
MCK_48 MCK divided by 48 (MCK up to 120MHz)
4
MCK_64 MCK divided by 64 (MCK up to 160MHz)
5
MCK_96 MCK divided by 96 (MCK up to 240MHz)
Bit 17 – RFCS Remove FCS
Writing this bit to '1' will cause received frames to be written to memory without their frame check
sequence (last 4 bytes). The indicated frame length will be reduced by four bytes in this mode.
Bit 16 – LFERD Length Field Error Frame Discard
Writing a '1' to this bit discards frames with a measured length shorter than the extracted length field (as
indicated by bytes 13 and 14 in a non-VLAN tagged frame). This only applies to frames with a length field
less than 0x0600.
Bits 15:14 – RXBUFO[1:0] Receive Buffer Offset
These bits determine the number of bytes by which the received data is offset from the start of the receive
buffer.
Bit 13 – PEN Pause Enable
When written to '1', transmission will pause if a non-zero 802.3 classic pause frame is received and PFC
has not been negotiated.
Bit 12 – RTY Retry Test
This bit must be written to '0' for normal operation.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 527