Datasheet

24.9.2 GMAC Network Configuration Register
Name: NCFGR
Offset: 0x004
Reset: 0x00080000
Property: R/W
Bit 31 30 29 28 27 26 25 24
IRXER RXBP IPGSEN IRXFCS EFRHD RXCOEN
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DCPF DBW[1:0] CLK[2:0] RFCS LFERD
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8
RXBUFO[1:0] PEN RTY MAXFS
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
UNIHEN MTIHEN NBC CAF JFRAME DNVLAN FD SPD
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 30 – IRXER Ignore IPG GRXER
When this bit is written to '1', the Receive Error signal (GRXER) has no effect on the GMAC operation
when Receive Data Valid signal (GRXDV) is low.
Bit 29 – RXBP Receive Bad Preamble
When written to '1', frames with non-standard preamble are not rejected.
Bit 28 – IPGSEN IP Stretch Enable
Writing a '1' to this bit allows the transmit IPG to increase above 96 bit times, depending on the previous
frame length using the IPG Stretch Register.
Bit 26 – IRXFCS Ignore RX FCS
For normal operation this bit must be written to zero.
When this bit is written to '1', frames with FCS/CRC errors will not be rejected. FCS error statistics will still
be collected for frames with bad FCS, and FCS status will be recorded in the DMA descriptor of the
frame.
Bit 25 – EFRHD Enable Frames Received in half-duplex
Writing a '1' to this bit enables frames to be received in half-duplex mode while transmitting.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 526