Datasheet

Bit 3 – TXEN Transmit Enable
Writing a '1' to this bit enables the GMAC transmitter to send data.
Writing a '0' to this bit stops transmission immediately, the transmit pipeline and control registers is
cleared, and the Transmit Queue Pointer Register will be set to point to the start of the transmit descriptor
list.
Value Description
0
Transmit is disabled
1
Transmit is enabled
Bit 2 – RXEN Receive Enable
Writing a '1' to this bit enables the GMAC to receive data.
Writing a '0' to this bit stops frame reception immediately, and the receive pipeline is cleared. The Receive
Queue Pointer Register is not affected.
Value Description
0
Receive is disabled
1
Receive is enabled
Bit 1 – LBL Loop Back Local
Writing '1' to this bit connects GTX to GRX, GTXEN to GRXDV, and forces full duplex mode.
GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is
important that receive and transmit circuits have already been disabled when making the switch into and
out of internal loop back.
Value Description
0
Loop back local is disabled
1
Loop back local is enabled
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 525