Datasheet

24.9.1 GMAC Network Control Register
Name: NCR
Offset: 0x000
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
LPI FNP TXPBPF ENPBPR
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SRTSM TXZQPF TXPF THALT TSTART BP
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 19 – LPI Low Power Idle Enable
Writing a '1' to this bit will enable low power idle (LPI) transmission, immediately transmitted on txd and
tx_er.
Bit 18 – FNP Flush Next Packet
Writing a '1' to this bit will flush the next packet from the external RX DPRAM. Flushing the next packet
will only take effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.
Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame
Takes the values stored in the Transmit PFC Pause Register.
Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception
Writing a '1' to this bit enables PFC Priority Based Pause Reception capabilities, enabling PFC
negotiation and recognition of priority-based pause frames.
Value Description
0
Normal operation
1
PFC Priority-based Pause frames are recognized
Bit 15 – SRTSM Store Receive Time Stamp to Memory
Writing a '1' to this bit causes the CRC of every received frame to be replaced with the value of the
nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time
stamp point.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 523