Datasheet

Table Of Contents
24.8 Register Summary
Offset Name Bit Pos.
0x00 NCR
7:0 WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL
15:8 SRTSM TXZQPF TXPF THALT TSTART BP
23:16 LPI FNP TXPBPF ENPBPR
31:24
0x04 NCFGR
7:0 UNIHEN MTIHEN NBC CAF JFRAME DNVLAN FD SPD
15:8 RXBUFO[1:0] PEN RTY MAXFS
23:16 DCPF DBW[1:0] CLK[2:0] RFCS LFERD
31:24 IRXER RXBP IPGSEN IRXFCS EFRHD RXCOEN
0x08 NSR
7:0 IDLE MDIO
15:8
23:16
31:24
0x0C UR
7:0 MII
15:8
23:16
31:24
0x10 DCFGR
7:0 ESPA ESMA FBLDO[4:0]
15:8 TXCOEN TXPBMS RXBMS[1:0]
23:16 DRBS[7:0]
31:24 DDRP
0x14 TSR
7:0 UND TXCOMP TFC TXGO RLE COL UBR
15:8 HRESP
23:16
31:24
0x18 RBQB
7:0 ADDR[5:0]
15:8 ADDR[13:6]
23:16 ADDR[21:14]
31:24 ADDR[29:22]
0x1C TBQB
7:0 ADDR[5:0]
15:8 ADDR[13:6]
23:16 ADDR[21:14]
31:24 ADDR[29:22]
0x20 RSR
7:0 HNO RXOVR REC BNA
15:8
23:16
31:24
0x24 ISR
7:0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS
15:8 PFTR PTZ PFNZ HRESP ROVR
23:16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR
31:24 TSUCMP WOL SRI PDRSFT PDRQFT
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 512