Datasheet

ManualsBrandsSeeedStudio ManualsInternet of Things (IoT)Wio Terminal ATSAMD51 Core w/ Realtek RTL8720DN BLE 5 & Wi-Fi 2.4G/5G Dev Board

501

502

503

504

505

506

507

508

509

510

Table Of Contents

receive buffer not available interrupt is set. If the frame is not successfully received, a statistics register is

incremented and the frame is discarded without informing software.

24.7.2 Statistics Registers

Statistics registers are described in the User Interface beginning with Section 1.8.48 ”GMAC Octets

Transmitted Low Register” and ending with Section 1.8.92 ”GMAC UDP Checksum Errors Register”.

The statistics register block begins at 0x100 and runs to 0x1B0, and comprises the registers listed below.

Octets Transmitted Low Register Broadcast Frames Received Register

Octets Transmitted High Register Multicast Frames Received Register

Frames Transmitted Register Pause Frames Received Register

Broadcast Frames Transmitted Register 64 Byte Frames Received Register

Multicast Frames Transmitted Register 65 to 127 Byte Frames Received Register

Pause Frames Transmitted Register 128 to 255 Byte Frames Received Register

64 Byte Frames Transmitted Register 256 to 511 Byte Frames Received Register

65 to 127 Byte Frames Transmitted Register 512 to 1023 Byte Frames Received Register

128 to 255 Byte Frames Transmitted Register 1024 to 1518 Byte Frames Received Register

256 to 511 Byte Frames Transmitted Register 1519 to Maximum Byte Frames Received

512 to 1023 Byte Frames Transmitted Register Undersize Frames Received Register

1024 to 1518 Byte Frames Transmitted Register Oversize Frames Received Register

Greater Than 1518 Byte Frames Transmitted

Jabbers Received Register

Transmit Underruns Register Frame Check Sequence Errors Register

Single Collision Frames Register Length Field Frame Errors Register

Multiple Collision Frames Register Receive Symbol Errors Register

Excessive Collisions Register Alignment Errors Register

Late Collisions Register Receive Resource Errors Register

Deferred Transmission Frames Register Receive Overrun Register

Carrier Sense Errors Register IP Header Checksum Errors Register

Octets Received Low Register TCP Checksum Errors Register

Octets Received High Register UDP Checksum Errors Register

Frames Received Register

These registers reset to zero on a read and stick at all ones when they count to their maximum value.

They should be read frequently enough to prevent loss of data.

The receive statistics registers are only incremented when the receive enable bit (RXEN) is set in the

Network Control register.

SAM D5x/E5x Family Data Sheet

GMAC - Ethernet MAC

Datasheet

DS60001507E-page 510