Datasheet

The Management Data Clock (MDC) should not toggle faster than 2.5 MHz (minimum period of 400 ns),
as defined by the IEEE 802.3 standard. MDC is generated by dividing down MCK. Three bits in the
Network Configuration register determine by how much MCK should be divided to produce MDC.
24.7.1.6 Interrupts
There are 18 interrupt conditions that are detected within the GMAC. The conditions are ORed to make a
single interrupt. Depending on the overall system design this may be passed through a further level of
interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt
handler. Refer to the device interrupt controller documentation to identify that it is the GMAC that is
generating the interrupt. To ascertain which interrupt, read the Interrupt Status register. Note that in the
default configuration this register will clear itself after being read, though this may be configured to be
write-one-to-clear if desired.
At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable register with the
pertinent interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable register with the pertinent
interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read Interrupt Mask register. If
the bit is set to 1, the interrupt is disabled.
24.7.1.7 Transmitting Frames
The procedure to set up a frame for transmission is the following:
1. Enable transmit in the Network Control register.
2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying
byte lengths can be used if they conclude on byte borders.
3. Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer
descriptor entries and control and length to word one.
4. Write data for transmission into the buffers pointed to by the descriptors.
5. Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer.
6. Enable appropriate interrupts.
7. Write to the transmit start bit (TSTART) in the Network Control register.
24.7.1.8 Receiving Frames
When a frame is received and the receive circuits are enabled, the GMAC checks the address and, in the
following cases, the frame is written to system memory:
• If it matches one of the four Specific Address registers.
• If it matches one of the four type ID registers.
• If it matches the hash address function.
• If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
• If the GMAC is configured to “copy all frames”.
The register receive buffer queue pointer points to the next entry in the receive buffer descriptor list and
the GMAC uses this as the address in system memory to write the frame to.
Once the frame has been completely and successfully received and written to system memory, the
GMAC then updates the receive buffer descriptor entry (see Table 1-6 “Receive Buffer Descriptor Entry”)
with the reason for the address match and marks the area as being owned by software. Once this is
complete, a receive complete interrupt is set. Software is then responsible for copying the data to the
application area and releasing the buffer (by writing the ownership bit back to 0).
If the GMAC is unable to write the data at a rate to match the incoming frame, then a receive overrun
interrupt is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, a
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 509