Datasheet

3. Mark the last descriptor in the queue with the wrap bit (bit 1 in word 0 set to 1).
4. Write address of receive buffer descriptor list and control information to GMAC register receive
buffer queue pointer
5. The receive circuits can then be enabled by writing to the address recognition registers and the
Network Control register.
24.7.1.3 Transmit Buffer List
Transmit data is read from areas of data (the buffers) in system memory. These buffers are listed in
another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a
sequence of descriptor entries as defined in Table 1-7 “Transmit Buffer Descriptor Entry”.
The Transmit Buffer Queue Pointer register points to this data structure.
To create this list of buffers:
1. Allocate a number (N) of buffers of between 1 and 2047 bytes of data to be transmitted in system
memory. Up to 128 buffers per frame are allowed.
2. Allocate an area 8N bytes for the transmit buffer descriptor list in system memory and create N
entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 31 of word 1 set to 0.
3. Mark the last descriptor in the queue with the wrap bit (bit 30 in word 1 set to 1).
4. Write address of transmit buffer descriptor list and control information to GMAC register transmit
buffer queue pointer.
5. The transmit circuits can then be enabled by writing to the Network Control register.
24.7.1.4 Address Matching
The GMAC register pair hash address and the four Specific Address register pairs must be written with
the required values. Each register pair comprises of a bottom register and top register, with the bottom
register being written first. The address matching is disabled for a particular register pair after the bottom
register has been written and re-enabled when the top register is written. Each register pair may be
written at any time, regardless of whether the receive circuits are enabled or disabled.
As an example, to set Specific Address register 1 to recognize destination address 21:43:65:87:A9:CB,
the following values are written to Specific Address register 1 bottom and Specific Address register 1 top:
• Specific Address register 1 bottom bits 31:0 (0x98): 0x8765_4321.
• Specific Address register 1 top bits 31:0 (0x9C): 0x0000_CBA9.
24.7.1.5 PHY Maintenance
The PHY Maintenance register is implemented as a shift register. Writing to the register starts a shift
operation which is signalled as complete when bit two is set in the Network Status register (about 2000
MCK cycles later when bits 18:16 are set to 010 in the Network Configuration register). An interrupt is
generated as this bit is set.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO
pin with each Management Data Clock (MDC) cycle. This causes the transmission of a PHY management
frame on MDIO. See section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation will return the current contents of the shift register. At the end of the
management operation the bits will have shifted back to their original locations. For a read operation the
data bits are updated with data read from the PHY. It is important to write the correct values to the register
to ensure a valid PHY management frame is produced.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 508