Datasheet

The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register
decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt
is also set when a zero quantum pause frame is received.
24.6.16.2 802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the
Network Control register. If either bit 11 or bit 12 of the Network Control register is written with logic 1, an
802.3 pause frame will be transmitted, providing full duplex is selected in the Network Configuration
register and the transmit block is enabled in the Network Control register.
Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between
the current frame and the next frame due to be transmitted.
Transmitted pause frames comprise the following:
• A destination address of 01-80-C2-00-00-01
• A source address taken from Specific Address register 1
• A type ID of 88-08 (MAC control frame)
• A pause opcode of 00-01
• A pause quantum register
• Fill of 00 to take the frame to minimum frame length
• Valid FCS
The pause quantum used in the generated frame will depend on the trigger source for the frame as
follows:
• If bit 11 is written with a '1', the pause quantum will be taken from the Transmit Pause Quantum
register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause
quantum as default.
• If bit 12 is written with a '1', the pause quantum will be zero.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status
register) and the only statistics register that will be incremented will be the Pause Frames Transmitted
register.
Pause frames can also be transmitted by the MAC using normal frame transmission methods.
24.6.17 Energy Efficient Ethernet Support
Features
• Energy Efficient Ethernet according to IEEE 802.3az
• A system’s transmit path can enter a low power mode if there is nothing to transmit.
• A PHY can detect whether its link partner’s transmit path is in low power mode, and configure its own
receive path to enter low power mode.
• Link remains up during lower power mode and no frames are dropped.
• Asymmetric, one direction can be in low power mode while the other is transmitting normally.
• LPI (Low Power Idle) signaling is used to control entry and exit to and from low power modes.
Note: LPI signaling can only take place if both sides have indicated support for it through auto-
negotiation.
Operation
• Low power control is done at the MII (reconciliation sublayer).
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 505