Datasheet

There are eight additional 80-bit registers that capture the time at which PTP event frames are
transmitted and received. An interrupt is issued when these registers are updated. The TSU timer count
value can be compared to a programmable comparison value. For the comparison, the 48 bits of the
seconds value and the upper 22 bits of the nanoseconds value are used. A signal (GTSUCOMP) is
output from the core to indicate when the TSU timer count value is equal to the comparison value stored
in the TSU timer comparison value registers (GMAC.NSC, GMAC.SCL, and GMAC.SCH). An interrupt
can also be generated (if enabled) when the TSU timer count value and comparison value are equal,
mapped to bit 29 of the interrupt status register.
24.6.16 MAC 802.3 Pause Frame Support
Note: Refer to the Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description
of MAC 802.3 pause operation.
The following table shows the start of a MAC 802.3 pause frame.
Table 24-13. Start of an 802.3 Pause Frame
Address Type
(MAC Control Frame)
Pause
Destination Source Opcode Time
0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes
The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame,
and hardware generated pause frame transmission.
24.6.16.1 802.3 Pause Frame Reception
The bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set,
transmission will pause if a non zero pause quantum frame is received.
If a valid pause frame is received, then the Pause Time register is updated with the new frame's pause
time, regardless of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of
the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has
been enabled (bit 12 and bit 13 of the Interrupt Mask register). Pause frames received with non zero
quantum are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames received
with zero quantum are indicated on bit 13 of the Interrupt Status register.
Once the Pause Time register is loaded and the frame currently being transmitted has been sent, no new
frames are transmitted until the pause time reaches zero. The loading of a new pause time, and hence
the pausing of transmission, only occurs when the GMAC is configured for full duplex operation. If the
GMAC is configured for half duplex there will be no transmission pause, but the pause frame received
interrupt will still be triggered. A valid pause frame is defined as having a destination address that
matches either the address stored in Specific Address register ‘1’ or if it matches the reserved address of
0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause
opcode of 0x0001.
Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be
discarded. Valid pause frames received will increment the pause frames received statistic register.
The pause time register decrements every 512 bit times once the transmission has stopped. For test
purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes the
Pause Time register to decrement every GTXCK cycle once transmission has stopped.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 504