Datasheet

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Frame Segment Value
Version PTP (Octet 15) 02
24.6.15 Time Stamp Unit
Overview
The TSU consists of a timer and registers to capture the time at which PTP event frames cross the
message timestamp point. An interrupt is issued when a capture register is updated.
The 1588 time stamp unit (TSU) is implemented as a 94-bit timer.
• The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer
Seconds High Register” (TSH) and GMAC 1588 Timer Seconds Low Register (TSL).
• The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588
Timer Nanoseconds Register (TN).
• The lowest 16 bits [15:0] of the timer count sub-nanoseconds.
The 46 lower bits roll over when they have counted to 1s. An interrupt is generated when the seconds
increment. The timer increments by a programmable period (to approximately 15.2fs resolution) with each
MCK period. The timer value can be read, written and adjusted with 1ns resolution (incremented or
decremented) through the APB interface.
Timer Adjustment
The amount by which the timer increments each clock cycle is controlled by the Timer Increment register
(TI). Bits [7:0] are the default increment value in nanoseconds. Additional 16 bits of sub-nanosecond
resolution are available using the Timer Increment Sub-Nanoseconds register (TISUBN). If the rest of the
register is written with zero, the timer increments by the value in [7:0], plus the value of the TISUBN for
each clock cycle.
The TISUBN allows a resolution of approximately 15fs.
Bits [15:8] of the increment register are the alternative increment value in nanoseconds, and bits [23:16]
are the number of increments after which the alternative increment value is used. If [23:16] are zero the
alternative increment value will never be used.
Taking the example of 10.2MHz, there are 102 cycles every 10µs or 51 cycles every 5µs.
So a timer with a 10.2MHz clock source is constructed by incrementing by 98ns for fifty
cycles and then incrementing by 100ns (98ns × 50 + 100ns = 5000ns). This is
programmed by writing the value 0x00326462 to the Timer Increment register (TI).
In a second example, a 49.8 MHz clock source requires 20ns for 248 cycles, followed by
an increment of 40ns (20ns × 248 + 40ns = 5000ns). This is programmed by writing the
value 0x00F82814 to the TI register.
The Number of Increments bit field in the TI register is 8 bit in size, so frequencies up to 50MHz are
supported with 200kHz resolution.
Without the alternative increment field the period of the clock would be limited to an integer number of
nanoseconds, resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250
MHz.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 503