Datasheet

18. PM – Power Manager
7.3.1 Starting of Internal Regulator
After power-up, the device is set to its initial state and kept in Reset, until the power has stabilized
throughout the device.
The internal regulator provides VDDCORE. Once the external voltage VDDIO/VDDANA and VDDCORE
reach a stable value, the internal Reset is released.
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18. PM – Power Manager
7.3.2 Starting of Clocks
Once the power has stabilized and the internal Reset is released, the device will use a 48MHz clock by
default. The clock source for this clock signal is DFLL48M, which is enabled after a reset by default. This
is also the default time base for Generic Clock Generator 0. In turn, Generator 0 provides the main clock
GCLK_MAIN which is used by the Main Clock module (MCLK).
Some synchronous system clocks are active after Start-Up, allowing software execution. Refer to the
“Clock Mask Registers” section in the MCLK-Main Clock documentation for the list of clocks that are
running by default. Synchronous system clocks that are running receive the 48MHz clock from Generic
Clock Generator 0. Other generic clocks are disabled.
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18. PM – Power Manager
7.3.3 I/O Pins
After power-up, the I/O pins are tri-stated except PA30, which is pull-up enabled and configured as input
in order to serve as part of the debug interface.
7.3.4 Fetching of Initial Instructions
After Reset has been released, the CPU starts fetching PC and SP values from the Reset address,
0x00000000. This points to the first executable address in the internal Flash memory. The code read from
the internal Flash can be used to configure the clock system and clock sources. See the related
peripheral documentation for details. Refer to the ARM Architecture Reference Manual for more
information on CPU startup (http://www.arm.com).
7.4 Power-On Reset and Brown-Out Detector
The SAM D5x/E5x embeds three features to monitor, warn and/or reset the device:
• POR: Power-on Reset on the main supply VDD (VDDANA/VSWOUT).
• BOD33: Brown-out detector on VSWOUT/VBAT
• Brown-out detector internal to the voltage regulator for VDDCORE. BOD12 is calibrated in production
and its calibration parameters are stored in the NVM User Row. This data should not be changed if
the User Row is written to in order to assure correct behavior.
7.4.1 Power-On Reset on VSWOUT
VSWOUT is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If
VSWOUT goes below the threshold voltage, the entire chip is reset.
SAM D5x/E5x Family Data Sheet
Power Supply and Start-Up ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 50