Datasheet

frame will still be transmitted but without the checksum substitution, as typically the reason that the
substitution did not occur was that the protocol was not recognized.
24.6.7 MAC Filtering Block
The filter block determines which frames should be written to the FIFO interface and on to the DMA.
Whether a frame is passed depends on what is enabled in the Network Configuration register, the state of
the external matching pins, the contents of the specific address, type and Hash registers and the frame's
destination address and type field.
If bit 25 of the Network Configuration register is not set, a frame will not be copied to memory if the GMAC
is transmitting in half duplex mode at the time a destination address is received.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an
Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB
of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for
unicast. The all ones address is the broadcast address and a special case of multicast.
The GMAC supports recognition of four specific addresses. Each specific address requires two registers,
Specific Address register Bottom and Specific Address register Top. Specific Address register Bottom
stores the first four bytes of the destination address and Specific Address register Top contains the last
two bytes. The addresses stored can be specific, group, local or universal.
The destination address of received frames is compared against the data stored in the Specific Address
registers once they have been activated. The addresses are deactivated at reset or when their
corresponding Specific Address register Bottom is written. They are activated when Specific Address
register Top is written. If a receive frame address matches an active address, the frame is written to the
FIFO interface and on to DMA memory.
Frames may be filtered using the type ID field for matching. Four type ID registers exist in the register
address space and each can be enabled for matching by writing a one to the MSB (bit 31) of the
respective register. When a frame is received, the matching is implemented as an OR function of the
various types of match.
The contents of each type ID register (when enabled) are compared against the length/type ID of the
frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and
copied to memory if a match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the
receive buffer descriptor status are set indicating which type ID register generated the match, if the
receive checksum offload is disabled.
The reset state of the type ID registers is zero, hence each is initially disabled.
The following example illustrates the use of the address and type ID match registers for a MAC address
of 21:43:65:87:A9:CB:
Preamble 55
SFD D5
DA (Octet 0 - LSB) 21
DA (Octet 1) 43
DA (Octet 2) 65
DA (Octet 3) 87
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 494