Datasheet

By setting when bit 28 is set in the Network Configuration register, the Inter Packet Gap (IPG) may be
stretched beyond 96 bits depending on the length of the previously transmitted frame and the value
written to the IPG Stretch register (IPGS). The least significant 8 bits of the IPG Stretch register multiply
the previous frame length (including preamble). The next significant 8 bits (+1 so as not to get a divide by
zero) divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when
bit 28 is set in the Network Configuration register. The IPG Stretch register cannot be used to shrink the
IPG below 96 bits.
If the back pressure bit is set in the Network Control register, or if the HDFC configuration bit is set in the
UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a
collision. This provides a way of implementing flow control in half duplex mode.
24.6.5 MAC Receive Block
All processing within the MAC receive block is implemented using a 16-bit data path. The MAC receive
block checks for valid preamble, FCS, alignment and length, presents received frames to the FIFO
interface and stores the frame destination address for use by the address checking block.
If, during the frame reception, the frame is found to be too long, a bad frame indication is sent to the FIFO
interface. The receiver logic ceases to send data to memory as soon as this condition occurs.
At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad.
The DMA block will recover the current receive buffer if the frame was bad.
Ethernet frames are normally stored in DMA memory complete with the FCS. Setting the FCS remove bit
in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The
reported frame length field is reduced by four bytes to reflect this operation.
The receive block signals to the register block to increment the alignment, CRC (FCS), short frame, long
frame, jabber or receive symbol errors when any of these exception conditions occur.
If bit 26 is set in the network configuration, CRC errors will be ignored and CRC errored frames will not be
discarded, though the Frame Check Sequence Errors statistic register will still be incremented.
Additionally, if not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1 will be
updated to indicate the FCS validity for the particular frame. This is useful for applications such as
EtherCAT whereby individual frames with FCS errors must be identified.
Received frames can be checked for length field error by setting the length field error frame discard bit of
the Network Configuration register (bit-16). When this bit is set, the receiver compares a frame's
measured length with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded
if the measured length is shorter. This checking procedure is for received frames between 64 bytes and
1518 bytes in length.
Each discarded frame is counted in the 10-bit length field error statistics register. Frames where the
length field is greater than or equal to 0x0600 hex will not be checked.
24.6.6 Checksum Offload for IP, TCP and UDP
The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and
transmit directions, which is enabled by setting bit 24 in the Network Configuration register for receive
and bit 11 in the DMA Configuration register for transmit.
IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement
sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the
16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header, the data and a
conceptual IP pseudo header.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 492