Datasheet

frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC
registers.
If Partial Store and Forward mode is active, the DMA will begin fetching the packet data before the status
is available. As soon as the status becomes available, the DMA will fetch this information as soon as
possible before continuing to fetch the remainder of the frame. Once the last frame data has been
transferred to the packet buffer, the status and statistics are updated to the GMAC registers.
24.6.4 MAC Transmit Block
The MAC transmitter can operate in either half duplex or full duplex mode and transmits frames in
accordance with the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the
IEEE 802.3 specification is followed.
A small input buffer receives data through the FIFO interface which will extract data in 32-bit form. All
subsequent processing prior to the final output is performed in bytes.
Transmit data can be output using the MII interface.
Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit
FIFO interface a word at a time.
If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-
bit polynomial. This is inverted and appended to the end of the frame taking the frame length to a
minimum of 64 bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit
frame, neither pad nor CRC are appended. The no CRC bit can also be set through the FIFO interface.
In full duplex mode (at all data rates), frames are transmitted immediately. Back to back frames are
transmitted at least 96 bit times apart to guarantee the interframe gap.
In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal
to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision
signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from
the data register and then retry transmission after the back off time has elapsed. If the collision occurs
during either the preamble or Start Frame Delimiter (SFD), then these fields will be completed prior to
generation of the jam sequence.
The back off time is based on an XOR of the 10 least significant bits of the data coming from the transmit
FIFO interface and a 10-bit pseudo random number generator. The number of bits used depends on the
number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the
maximum of 10 bits. All 10 bits are used above ten collisions. An error will be indicated and no further
attempts will be made if 16 consecutive attempts cause collision. This operation is compliant with the
description in Clause 4.2.3.2.5 of the IEEE 802.3 standard which refers to the truncated binary
exponential back off algorithm.
In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry will be
performed up to 16 times. This condition is reported in the transmit buffer descriptor word 1 (late collision,
bit 26) and also in the Transmit Status register (late collision, bit 7). An interrupt can also be generated (if
enabled) when this exception occurs, and bit 5 in the Interrupt Status register will be set.
In all modes of operation, if the transmit DMA underruns, a bad CRC is automatically appended using the
same mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system
this should never happen and also it is impossible if configured to use the DMA with packet buffers, as
the complete frame is buffered in local packet buffer memory.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 491