Datasheet

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Bit Function
16 No CRC to be appended by MAC. When set, this implies that the data in the buffers already
contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the
MAC.
This control bit must be set for the first buffer in a frame and will be ignored for the subsequent
buffers of a frame.
Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation
offload, otherwise checksum generation and substitution will not occur.
15 Last buffer, when set this bit will indicate the last buffer in the current frame has been reached.
14 Reserved
13:0 Length of buffer
To transmit frames, the buffer descriptors must be initialized by writing an appropriate Byte address to bits
[31:0] of the first word of each descriptor list entry.
The second word of the transmit buffer descriptor is initialized with control information that indicates the
length of the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in
the frame.
After transmission the status bits are written back to the second word of the first buffer along with the
used bit. Bit 31 is the used bit which must be zero when the control word is read if transmission is to take
place. It is written to '1' once the frame has been transmitted. Bits[29:20] indicate various transmit error
conditions. Bit 30 is the wrap bit which can be set for any buffer within a frame. If no wrap bit is
encountered the queue pointer continues to increment.
The Transmit Buffer Queue Base Address register can only be updated while transmission is disabled or
halted; otherwise any attempted write will be ignored. When transmission is halted the transmit buffer
queue pointer will maintain its value. Therefore when transmission is restarted the next descriptor read
from the queue will be from immediately after the last successfully transmitted frame. As long as transmit
is disabled by writing a '0' to the Transmit Enable bit in the Network Control register (NCR.TXEN), the
transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base
Address register (TBQB).
Note: Disabling receive does not have the same effect on the receive buffer queue pointer.
Once the transmit queue is initialized, transmit is activated by writing a '1' to the Start Transmission bit of
the Network Control register (NCR.TSTART). Transmit is halted when a buffer descriptor with its used bit
set is read, a transmit error occurs, or by writing to the Transmit Halt bit of the Network Control register
(NCR.THALT). Transmission is suspended if a pause frame is received while the Transmit Pause Frame
bit is '1' in the Network Configuration register (NCR.TXPF). Rewriting the Start bit (NCR.TSTART) while
transmission is active is allowed. This is implemented by the Transmit Go variable which is readable in
the Transmit Status register (TSR.TXGO). The TXGO variable is reset when:
• Transmit is disabled.
• A buffer descriptor with its ownership bit set is read.
• Bit 10, THALT, of the Network Control register is written.
• There is a transmit error such as too many retries or a transmit underrun.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 487