Datasheet

rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128
Bytes for the receive buffers size.
When in packet buffer full store and forward mode, only good received frames are written out of the DMA,
so no fragments will exist in the AHB buffers due to MAC receiver errors. There is still the possibility of
fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame.
If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the
location of the receive AHB buffer, the buffer has been already used and cannot be used again until
software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit in the
receive status register is set and an interrupt triggered. The receive resource error statistics register is
also incremented.
When the DMA is configured in the packet buffer full store and forward mode, the user can optionally
select whether received frames should be automatically discarded when no AHB buffer resource is
available. This feature is selected via the DMA Discard Receive Packets bit in the DMA Configuration
register (DCFGR.DDRP). By default, the received frames are not automatically discarded. If this feature is
off, then received packets will remain to be stored in the SRAM-based packet buffer until AHB buffer
resource next becomes available. This may lead to an eventual packet buffer overflow if packets continue
to be received when bit zero (used bit) of the receive buffer descriptor remains set.
Note: After a used bit has been read, the receive buffer manager will re-read the location of the receive
buffer descriptor every time a new packet is received. When the DMA is not configured in the packet
buffer full store and forward mode and a used bit is read, the frame currently being received will be
automatically discarded.
When the DMA is configured in the packet buffer full store and forward mode, a receive overrun condition
occurs when the receive SRAM-based packet buffer is full, or because HRESP was not OK. In all other
modes, a receive overrun condition occurs when either the AHB bus was not granted quickly enough, or
because HRESP was not OK, or because a new frame has been detected by the receive block, but the
status update or write back for the previous frame has not yet finished. For a receive overrun condition,
the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next
frame that is received whose address is recognized reuses the buffer.
In any packet buffer mode, writing a '1' to the Flush Next Package bit in the NCR register (NCR.FNP) will
force a packet from the external SRAM-based receive packet buffer to be flushed. This feature is only
acted upon when the RX DMA is not currently writing packet data out to AHB, i.e., it is in an IDLE state. If
the RX DMA is active, NCR.FNP=1 is ignored.
24.6.3.4 Transmit AHB Buffers
Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1
and 16384 Bytes long, so it is possible to transmit frames longer than the maximum length specified in
the IEEE 802.3 standard. It should be noted that zero length AHB buffers are allowed and that the
maximum number of buffers permitted for each transmit frame is 128.
The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors
at a location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is
set in software using the Transmit Buffer Queue Base Address register. Each list entry consists of two
words. The first is the Byte address of the transmit buffer and the second containing the transmit control
and status. For the packet buffer DMA, the start location for each AHB buffer is a Byte address, the
bottom bits of the address being used to offset the start of the data from the data-word boundary (i.e., bits
2,1 and 0 are used to offset the address for 64-bit data paths).
Frames can be transmitted with or without automatic Cyclic Redundancy Checksum (CRC) generation. If
CRC is automatically generated, pad will also be automatically generated to take frames to a minimum
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 485