Datasheet

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Bit Function
12:0 These bits represent the length of the received frame which may or may not include FCS
depending on whether FCS discard mode is enabled.
With FCS discard mode disabled: (bit 17 clear in Network Configuration Register)
Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12
bits are concatenated with bit[13] of the descriptor above.
With FCS discard mode enabled: (bit 17 set in Network Configuration Register)
Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled, these
12 bits are concatenated with bit[13] of the descriptor above.
Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can
be offset by up to three Bytes, depending on the value written to bits 14 and 15 of the Network
Configuration register (NCFGR). If the start location of the AHB buffer is offset, the available length of the
first AHB buffer is reduced by the corresponding number of Bytes.
To receive frames, the AHB buffer descriptors must be initialized by writing an appropriate address to bits
31:2 in the first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates
the last entry in the buffer descriptor list.
The start location of the receive buffer descriptor list must be written with the receive buffer queue base
address before reception is enabled (receive enable in the Network Control register NCR). Once
reception is enabled, any writes to the Receive Buffer Queue Base Address register (RBQB) are ignored.
When read, it will return the current pointer position in the descriptor list, though this is only valid and
stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA operation
starts writing data into the receive buffer. If an error occurs, the buffer is recovered.
An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible
through the CPU interface. The receive buffer queue pointer increments by two words after each buffer
has been used. It re-initializes to the receive buffer queue base address if any descriptor has its wrap bit
set.
As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the
descriptor to logic one indicating the AHB buffer has been used.
Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames
have been received, checking the start of frame and end of frame bits.
When the DMA is configured in the packet buffer Partial Store And Forward mode, received frames are
written out to the AHB buffers as soon as enough frame data exists in the packet buffer. For both cases,
this may mean several full AHB buffers are used before some error conditions can be detected. If a
receive error is detected the receive buffer currently being written will be recovered. Previous buffers will
not be recovered. As an example, when receiving frames with cyclic redundancy check (CRC) errors or
excessive length, it is possible that a frame fragment might be stored in a sequence of AHB receive
buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no
end of frame bit set.
To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater
than 128 Bytes with CRC errors. Collision fragments will be less than 128 Bytes long, therefore it will be a
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 484