Datasheet

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Bit Function
23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled.
With RX checksum offloading disabled: (bit 24 clear in Network Configuration)
Type ID register match. Encoded as follows:
00: Type ID register 1 match
01: Type ID register 2 match
10: Type ID register 3 match
11: Type ID register 4 match
If more than one Type ID is matched only one is indicated with priority 4 down to 1.
With RX checksum offloading enabled: (bit 24 set in Network Configuration Register)
00: Neither the IP header checksum nor the TCP/UDP checksum was checked.
01: The IP header checksum was checked and was correct. Neither the TCP nor UDP checksum
was checked.
10: Both the IP header and TCP checksum were checked and were correct.
11: Both the IP header and UDP checksum were checked and were correct.
21 VLAN tag detected—type ID of 0x8100. For packets incorporating the stacked VLAN processing
feature, this bit will be set if the second VLAN tag has a type ID of 0x8100
20 Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating the
stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of
0x8100 and a null VLAN identifier.
19:17 VLAN priority—only valid if bit 21 is set.
16 Canonical format indicator (CFI) bit (only valid if bit 21 is set).
15 End of frame—when set the buffer contains the end of a frame. If end of frame is not set, then
the only valid status bit is start of frame (bit 14).
14 Start of frame—when set the buffer contains the start of a frame. If both bits 15 and 14 are set,
the buffer contains a whole frame.
13 This bit has a different meaning depending on whether jumbo frames and ignore FCS modes are
enabled. If neither mode is enabled this bit will be zero.
With jumbo frame mode enabled: (bit 3 set in Network Configuration Register) Additional bit for
length of frame (bit[13]), that is concatenated with bits[12:0]
With ignore FCS mode enabled and jumbo frames disabled: (bit 26 set in Network Configuration
Register and bit 3 clear in Network Configuration Register) This indicates per frame FCS status
as follows:
0: Frame had good FCS
1: Frame had bad FCS, but was copied to memory as ignore FCS enabled.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 483