Datasheet

Table Of Contents

Table 24-2. Receive Buffer Descriptor Entry

Bit Function

Word 0

31:2 Address of beginning of buffer

1 Wrap—marks last descriptor in receive buffer descriptor list.

0 Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets

this to one once it has successfully written a frame to memory.

Software has to clear this bit before the buffer can be used again.

Word 1

31 Global all ones broadcast address detected

30 Multicast hash match

29 Unicast hash match

28 –

27 Specific Address Register match found, bit 25 and bit 26 indicate which Specific Address

26:25 Specific Address Register match. Encoded as follows:

00: Specific Address Register 1 match

01: Specific Address Register 2 match

10: Specific Address Register 3 match

11: Specific Address Register 4 match

If more than one specific address is matched only one is indicated with priority 4 down to 1.

24 This bit has a different meaning depending on whether RX checksum offloading is enabled.

With RX checksum offloading disabled: (bit 24 clear in Network Configuration Register)

Type ID register match found, bit 22 and bit 23 indicate which type ID register causes the match.

With RX checksum offloading enabled: (bit 24 set in Network Configuration Register)

0: The frame was not SNAP encoded and/or had a VLAN tag with the Canonical Format

Indicator (CFI) bit set.

1: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not

set.

SAM D5x/E5x Family Data Sheet

GMAC - Ethernet MAC

Datasheet

DS60001507E-page 482