Datasheet

• Support for Transmit TCP/IP checksum offload
• Support for priority queuing
• When a collision on the line occurs during transmission, the packet will be automatically replayed
directly from the packet buffer memory rather than having to re-fetch through the AHB (full store and
forward ONLY)
• Received erroneous packets are automatically dropped before any of the packet is presented to the
AHB (full store and forward ONLY), thus reducing AHB activity
• Supports manual RX packet flush capabilities
• Optional RX packet flush when there is lack of AHB resource
24.6.3.2 Partial Store and Forward Using Packet Buffer DMA
The DMA uses SRAM-based packet buffers, and can be programmed into a low latency mode, known as
Partial Store and Forward. This mode allows for a reduced latency as the full packet is not buffered
before forwarding.
Note: This option is only available when the device is configured for full duplex operation.
This feature is enabled via the programmable TX and RX Partial Store and Forward registers (TPSF and
RPSF). When the transmit Partial Store and Forward mode is activated, the transmitter will only begin to
forward the packet to the MAC when there is enough packet data stored in the packet buffer. Likewise,
when the receive Partial Store and Forward mode is activated, the receiver will only begin to forward the
packet to the AHB when enough packet data is stored in the packet buffer. The amount of packet data
required to activate the forwarding process is programmable via watermark registers. These registers are
located at the same address as the partial store and forward enable bits.
Note: The minimum operational value for the TX partial store and forward watermark is 20. There is no
operational limit for the RX partial store and forward watermark.
Enabling Partial Store and Forward is a useful means to reduce latency, but there are performance
implications. The GMAC DMA uses separate transmit and receive lists of buffer descriptors, with each
descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and
scattered around the AHB memory space.
24.6.3.3 Receive AHB Buffers
Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The
receive buffer depth is programmable in the range of 64 Bytes to 16 KBytes through the DMA
Configuration register (DCFGR), with the default being 128 Bytes.
The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors at
an address location pointed to by the receive buffer queue pointer. The base address for the receive
buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register
(RBQB).
Each list entry consists of two words. The first is the address of the receive AHB buffer and the second
the receive status.
If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is
written with zeroes except for the “Start of Frame” bit, which is always set for the first buffer in a frame.
Bit zero of the address field is written to 1 to show that the buffer has been used. The receive buffer
manager then reads the location of the next receive AHB buffer and fills that with the next part of the
received frame data. AHB buffers are filled until the frame is complete and the final buffer descriptor
status word contains the complete frame status. See the following table for details of the receive buffer
descriptor list.
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 481