Datasheet

31. EVSYS – Event System
24.6 Functional Description
24.6.1 Media Access Controller
The Transmit Block of the Media Access Controller (MAC) takes data from FIFO, adds preamble, checks
and adds padding and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of
operation are supported.
When operating in half duplex mode, the MAC Transmit Block generates data according to the Carrier
Sense Multiple Access with Collision Detect (CSMA/CD) protocol. The start of transmission is deferred if
Carrier Sense (CRS) is active. If Collision (COL) is detected during transmission, a jam sequence is
asserted and the transmission is retried after a random back off. The CRS and COL signals have no
effect in full duplex mode.
The Receive Block of the MAC checks for valid preamble, FCS, alignment and length, and presents
received frames to the MAC address checking block and FIFO. Software can configure the GMAC to
receive jumbo frames of up to 10240 Bytes. It can optionally strip CRC (Cyclic Redundancy Check) from
the received frame before transferring it to FIFO.
The Address Checker recognizes four specific 48-bit addresses, can recognize four different types of ID
values, and contains a 64-bit Hash register for matching multicast and unicast addresses as required. It
can recognize the broadcast address all-'1' (0xFFFFFFFFFFFF) and copy all frames. The MAC can also
reject all frames that are not VLAN tagged, and recognize Wake on LAN events.
The MAC Receive Block supports offloading of IP, TCP and UDP checksum calculations (both IPv4 and
IPv6 packet types supported), and can automatically discard bad checksum frames.
24.6.2 IEEE 1588 Time Stamp Unit
The IEEE 1588 time stamp unit (TSU) is implemented as a 94-bit timer.
• The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer
Seconds High Register” (TSH) and GMAC 1588 Timer Seconds Low Register (TSL).
• The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588
Timer Nanoseconds Register (TN).
• The lowest 16 bits [15:0] of the timer count sub-nanoseconds.
The 46 lower bits roll over when they have counted to 1s. The timer increments by a programmable
period (to approximately 15.2fs resolution) with each MCK period and can also be adjusted in 1ns
resolution (incremented or decremented) through APB register accesses.
24.6.3 AHB Direct Memory Access Interface
The GMAC DMA controller is connected to the MAC FIFO interface and provides a scatter-gather type
capability for packet data storage.
The DMA implements packet buffering where dual-port memories are used to buffer multiple frames.
24.6.3.1 Packet Buffer DMA
• Easier to guarantee maximum line rate due to the ability to store multiple frames in the packet buffer,
where the number of frames is limited by the amount of packet buffer memory and Ethernet frame
size
• Full store and forward, or partial store and forward programmable options (partial store will cater for
shorter latency requirements)
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 480