Datasheet

23.8.10 External Interrupt Sense Configuration n
Name: CONFIG
Offset: 0x1C + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter Enable x [x=7..0]
Note: The filter must be disabled if the asynchronous detection is enabled.
Value Description
0
Filter is disabled for EXTINT[n*8+x] input.
1
Filter is enabled for EXTINT[n*8+x] input.
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x=7..0]
These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated.
Value Name Description
0x0
NONE No detection
0x1
RISE Rising-edge detection
0x2
FALL Falling-edge detection
0x3
BOTH Both-edge detection
0x4
HIGH High-level detection
0x5
LOW Low-level detection
0x6 -
0x7
- Reserved
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 472