Datasheet

23.8.6 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EXTINT[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EXTINT[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:0 – EXTINT[15:0] External Interrupt Enable
The bit x of EXTINT disables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt
EXTINTx.
Value Description
0
The external interrupt x is disabled.
1
The external interrupt x is enabled.
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 468