Datasheet

In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt
(NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register
(CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag
(NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. In
this mode, the EIC clock is required.
The Synchronous Edge Detection Mode can be used in Idle and Standby sleep modes.
In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable
interrupt (NMI) pins set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or
NMIFLAG) directly. In this mode, the EIC clock is not requested.
The asynchronous edge detection mode can be used in Idle and Standby sleep modes.
23.6.4.3 Interrupt Pin Debouncing
The external interrupt pin (EXTINT) edge detection can use a debouncer to improve input noise immunity.
When selected, the debouncer can work in the synchronous mode or the asynchronous mode, depending
on the configuration of the ASYNCH.ASYNCH[x] bit for the pin. The debouncer uses the EIC clock as
defined by the bit CTRLA.CKSEL to clock the debouncing circuitry. The debouncing time frame is set with
the debouncer prescaler DPRESCALER.DPRESCALERn, which provides the low frequency clock tick
that is used to reject higher frequency signals.
The debouncing mode for pin EXTINT x can be selected only if the Sense bits in the Configuration y
register (CONFIGy.SENSEx) are set to RISE, FALL or BOTH. If the debouncing mode for pin EXTINT x is
selected, the filter mode for that pin (CONFIGy.FILTENx) can not be selected.
The debouncer manages an internal “valid pin state” that depends on the external interrupt (EXTINT) pin
transitions, the debouncing mode and the debouncer prescaler frequency. The valid pin state reflects the
pin value after debouncing. The external interrupt pin (EXTINT) is sampled continously on EIC clock. The
sampled value is evaluated on each low frequency clock tick to detect a transitional edge when the
sampled value is different of the current valid pin state. The sampled value is evaluated on each EIC
clock when DPRESCALER.TICKON=0 or on each low frequency clock tick when
DPRESCALER.TICKON=1, to detect a bounce when the sampled value is equal to the current valid pin
state. Transitional edge detection increments the transition counter of the EXTINT pin, while bounce
detection resets the transition counter. The transition counter must exceed the transition count threshold
as defined by the DPRESCALER.STATESn bitfield. In the synchronous mode the threshold is 4 when
DPRESCALER.STATESn=0 or 8 when DPRESCALER.STATESn=1. In the asynchronous mode the
threshold is 4.
The valid pin state for the pins can be accessed by reading the register PINSTATE for both synchronous
or asynchronous debouncing mode.
Synchronous edge detection In this mode the external interrupt (EXTINT) pin is sampled continously on
EIC clock.
1. A pin edge transition will be validated when the sampled value is consistently different of the
current valid pin state for 4 (or 8 depending on bit DPRESCALER.STATESn) consecutive ticks of
the low frequency clock.
2. Any pin sample, at the low frequency clock tick rate, with a value opposite to the current valid pin
state will increment the transition counter.
3. Any pin sample, at EIC clock rate (when DPRESCALER.TICKON=0) or the low frequency clock tick
(when DPRESCALER.TICKON=1), with a value identical to the current valid pin state will return the
transition counter to zero.
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 457