Datasheet

23.6.3 External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or
both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing
the Input Sense x bits in the Config n register (CONFIG.SENSEx). The corresponding interrupt flag
(INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (23.8.8 INTFLAG) is set when the
interrupt condition is met.
When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a
new interrupt condition is met.
In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if
the EXTINTx pin still matches the interrupt condition.
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K.
Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIG.FILTENx) is written to '1'.
The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs
the value when two or more samples are equal.
Table 23-1. Majority Vote Filter
Samples [0, 1, 2] Filter Output
[0,0,0] 0
[0,0,1] 0
[0,1,0] 0
[0,1,1] 1
[1,0,0] 0
[1,0,1] 1
[1,1,0] 1
[1,1,1] 1
When an external interrupt is configured for level detection and when filtering is disabled, detection is
done asynchronously. Level detection and asynchronous edge detection does not require GCLK_EIC or
CLK_ULP32K, but interrupt and events can still be generated.
If filtering or synchronous edge detection or debouncing is enabled, the EIC automatically requests
GCLK_EIC or CLK_ULP32K to operate. The selection between these two clocks is done by writing the
Clock Selection bits in the Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK
module. In these modes the external pin is sampled at the EIC clock rate, thus pulses with duration lower
than two EIC clock periods may not be properly detected.
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 455