Datasheet

23.5.4 DMA
Not applicable.
23.5.5 Interrupts
There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for
Non-Maskable Interrupt (NMI).
The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires
the interrupt controller to be configured first.
The NMI interrupt request line is connected to the interrupt controller, but does not require the interrupt to
be configured.
Related Links
10.2 Nested Vector Interrupt Controller
23.5.6 Events
The events are connected to the Event System. Using the events requires the Event System to be
configured first.
Related Links
31. EVSYS – Event System
23.5.7 Debug Operation
When the CPU is halted in Debug mode, the EIC continues normal operation. If the EIC is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
23.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Flag Status and Clear register (INTFLAG)
• Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG)
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
23.5.9 Analog Connections
Not applicable.
23.6 Functional Description
23.6.1 Principle of Operation
The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to
the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering,
clocked by GCLK_EIC or by CLK_ULP32K.
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 453