Datasheet

23. EIC – External Interrupt Controller
23.1 Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each
interrupt line can be individually masked and can generate an interrupt on rising, falling, both edges, or on
high or low levels. Each external pin has a configurable filter to remove spikes. Also, each external pin
can be configured to be asynchronous in order to wake-up the device from Sleep modes where all clocks
have been disabled. External pins can generate an event.
A separate Non-Maskable Interrupt (NMI) is supported. It has properties similar to the other external
interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other Interrupt
mode.
23.2 Features
• Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
• Dedicated, Individually Maskable Interrupt for Each Pin
• Interrupt on Rising, Falling, or Both Edges
• Synchronous or Asynchronous Edge Detection mode
• Interrupt pin Debouncing
• Interrupt on High or Low Levels
• Asynchronous Interrupts for Sleep Modes Without Clock
• Filtering of External Pins
• Event Generation from EXTINTx
23.3 Block Diagram
Figure 23-1. EIC Block Diagram
Filter
Edge/Level
Detection
Interrupt
Wake
Event
FILTENx
EXTINTx
intreq_extint
inwake_extint
evt_extint
Filter
Edge/Level
Detection
Interrupt
Wake
NMIFILTEN
NMISENSE[2:0]
NMI
intreq_nmi
inwake_nmi
SENSEx[2:0]
SAM D5x/E5x Family Data Sheet
EIC – External Interrupt Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 451