Datasheet

22.8.20 Channel Interrupt Enable Clear
Name: CHINTENCLR
Offset: 0x4C + n*0x10 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
Bit 7 6 5 4 3 2 1 0
SUSP TCMPL TERR
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – SUSP Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel
Suspend interrupt.
Value Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the
Channel Transfer Complete interrupt.
Value Description
0
The Channel Transfer Complete interrupt is disabled. When block action is set to none, the
TCMPL flag will not be set when a block transfer is completed.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the
Channel Transfer Error interrupt.
Value Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 439