Datasheet

22.8.19 Channel Event Control
Name: CHEVCTRL
Offset: 0x46 + n*0x10 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
EVOE EVIE EVOMODE[1:0] EVACT[2:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – EVOE Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every
condition defined in the Channel Event Output Selection bits (CHEVCTRL.EVOMODE).
Value Description
0
Channel event generation is disabled.
1
Channel event generation is enabled.
Bit 6 – EVIE Channel Event Input Enable
Value Description
0
Channel event action will not be executed on any incoming event.
1
Channel event action will be executed on any incoming event.
Bits 5:4 – EVOMODE[1:0] Channel Event Output Mode
These bits define the channel event output selection. For details on event output generation, refer to
22.6.3.6 Event Output Selection.
Value Name Description
0x0
DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
0x1
TRIGACT Ongoing trigger action
0x2-0x3
Reserved
Bits 2:0 – EVACT[2:0] Channel Event Input Action
These bits define the event input action. The action is executed only if the corresponding EVIE bit in the
CHEVCTRL register of the channel is set. For details on event actions, refer to 22.6.3.5 Event Input
Actions. These bits are available only for channels with event input support.
Value Name Description
0x0
NOACT No action
0x1
TRIG Transfer and periodic transfer trigger
0x2
CTRIG Conditional transfer trigger
0x3
CBLOCK Conditional block transfer
0x4
SUSPEND Channel suspend operation
0x5
RESUME Channel resume operation
0x6
SSKIP Skip next block suspend action
0x7
INCPRI Increase priority
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 438