Datasheet

...........continued
Index Instance Channel Presentation
0x44 ADC0 RESRDY index of DMA RESRDY trigger
0x45 ADC0 SEQ Index of DMA SEQ trigger
0x46 ADC1 RESRDY Index of DMA RESRDY trigger
0x47 ADC1 SEQ Index of DMA SEQ trigger
0x49 - 0x48 DAC EMPTY DMA DAC Empty Req
0x4B - 0x4A DAC RESRDY DMA DAC Result Ready Req
0x4D - 0x4C I2S RX Indexes of DMA RX triggers
0x4F - 0x4E I2S TX Indexes of DMA TX triggers
0x50 PCC RX Indexes of PCC RX trigger
0x51 AES WR DMA DATA Write trigger
0x52 AES RD DMA DATA Read trigger
0x53 QSPI RX Indexes of QSPI RX trigger
0x54 QSPI TX Indexes of QSPI TX trigger
Bit 6 – RUNSTDBY Channel run in standby
This bit is used to keep the DMAC channel running in standby mode.
This bit is not enable-protected.
Value Description
0
The DMAC channel is halted in standby.
1
The DMAC channel continues to run in standby.
Bit 1 – ENABLE Channel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer
buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the
ongoing burst transfer is completed.
Writing a '1' to this bit will enable the DMA channel.
This bit is not enable-protected.
Value Description
0
DMA channel is disabled.
1
DMA channel is enabled.
Bit 0 – SWRST Channel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the
channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is
automatically cleared when the reset is completed.
Value Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 435