Datasheet

Value Name Description
0x7
8BEAT 8-beats burst length
0x8
9BEAT 9-beats burst length
0x9
10BEAT 10-beats burst length
0xA
11BEAT 11-beats burst length
0xB
12BEAT 12-beats burst length
0xC
13BEAT 13-beats burst length
0xD
14BEAT 14-beats burst length
0xE
15BEAT 15-beats burst length
0xF
16BEAT 16-beats burst length
Bits 21:20 – TRIGACT[1:0] Trigger Action
These bits define the trigger action used for a transfer.
These bits are not enable-protected.
Value Name Description
0x0
BLOCK One trigger required for each block transfer
0x1
Reserved
0x2
BURST One trigger required for each burst transfer
0x3
TRANSACTION One trigger required for each transaction
Bits 15:8 – TRIGSRC[7:0] Trigger Source
These bits define the peripheral that will be the source of a trigger.
Index Instance Channel Presentation
0x00 DISABLE Only software/event triggers
0x01 RTC TIMESTAMP DMA RTC timestamp trigger
0x02 DSU DCC0 DMAC ID for DCC0 register
0x03 DSU DCC1 DMAC ID for DCC1 register
0x04 SERCOM0 RX Index of DMA RX trigger
0x05 SERCOM0 TX Index of DMA TX trigger
0x06 SERCOM1 RX Index of DMA RX trigger
0x07 SERCOM1 TX Index of DMA TX trigger
0x08 SERCOM2 RX Index of DMA RX trigger
0x09 SERCOM2 TX Index of DMA TX trigger
0x0A SERCOM3 RX Index of DMA RX trigger
0x0B SERCOM3 TX Index of DMA TX trigger
0x0C SERCOM4 RX Index of DMA RX trigger
0x0D SERCOM4 TX Index of DMA TX trigger
0x0E SERCOM5 RX Index of DMA RX trigger
0x0F SERCOM5 TX Index of DMA TX trigger
0x10 SERCOM6 RX Index of DMA RX trigger
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 433